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(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 2.0 Rev. 2.1 Description Initial Issue Revised ISB1/IDR/Test Condition of ICC Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Adding SL Spec. Revised ABSOLUTE MAXIMUN RATINGS Added ISB1/IDR values when TA = 25 and TA = 40 Revised ISB1 (MAX) of SL grade Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised -35ns to -45ns Spec. Revised VDR Issue Date Aug.29.2005 Oct.31.2005 May.14.2007 Jul.26.2007 Mar.30.2009
Rev. 2.2
Sep.11.2009
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
FEATURES GENERAL DESCRIPTION
Fast access time : 45/55/70ns Low power consumption: Operating current : 50/40/30mA (TYP.) Standby current : 3A@5V(TYP.) LL/SL version 2A@3V(TYP.) SL version Single 4.5V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Green package available Package : 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 32-pin 450 mil SOP 32-pin 600 mil P-DIP The LY622568 is a 2,097,152-bit low power CMOS static random access memory organized as 262,144 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY622568 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY622568 operates from a single power supply of 4.5V ~ 5.5V and all inputs and outputs are fully TTL compatible
PRODUCT FAMILY
Product Family LY622568(LL) LY622568(LLE) LY622568(LLI) LY622568(SL) LY622568(SLE) LY622568(SLI) Operating Temperature 0 ~ 70 -20 ~ 80 -40 ~ 85 0 ~ 70 -20 ~ 80 -40 ~ 85 Vcc Range 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V Speed 45/55/70ns 45/55/70ns 45/55/70ns 45/55/70ns 45/55/70ns 45/55/70ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 3A@5V 50/40/30mA 3A@5V 50/40/30mA 3A@5V 50/40/30mA 2A@3V 3A@5V 50/40/30mA 2A@3V 3A@5V 50/40/30mA 2A@3V 3A@5V 50/40/30mA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection
Vcc Vss
A0 - A17 DQ0 - DQ7
DECODER 256Kx8 MEMORY ARRAY
CE#, CE2 WE# OE# VCC VSS NC
A0-A17
DQ0-DQ7
I/O DATA CIRCUIT
COLUMN I/O
CE# CE2 WE# OE#
CONTROL CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 32 31 30 29 28 Vcc A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
A11 A9 A8 A13 WE# CE2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
LY622568
SOP/P-DIP
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
LY622568
TSOP-I/STSOP
ABSOLUTE MAXIMUN RATINGS*
PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write
Note:
CE# H X L L L
CE2 X L H H H
OE# X X H L X
WE# X X H H L
I/O OPERATION High-Z High-Z High-Z DOUT DIN
SUPPLY CURRENT ISB1 ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC VIN VSS Output Leakage VCC VOUT VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. - 45 CE# = VIL and CE2 = VIH , ICC - 55 II/O = 0mA - 70 Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1s CE# = 0.2V and CE2VCC-0.2V, ICC1 II/O = 0mA Other pins at 0.2V or VCC - 0.2V LL/LLE/LLI *5 SL CE# VCC-0.2V 25 *5 SLE Standby Power or CE20.2V ISB1 *5 40 SLI Supply Current Others at 0.2V or VCC - 0.2V SL SLE/SLI
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 5. This parameter is measured at VCC = 3.0V
MIN. 4.5 2.4 - 0.2 -1 -1 2.4 -
TYP. 5.0 50 40 30 4 3 2 2 3 3
*4
MAX. 5.5 VCC+0.3 0.6 1 1 0.4 80 60 50 10 50 5 5 20 25
UNIT V V V A A V V mA mA mA mA A A A A A
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA = 25, f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 6 8
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY622568-45 MIN. MAX. 45 45 45 25 10 5 15 15 10 LY622568-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 LY622568-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 UNIT ns ns ns ns ns ns ns ns ns
SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
LY622568-45 MIN. MAX. 45 40 40 0 35 0 20 0 5 15
LY622568-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20
LY622568-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25
UNIT ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA Dout Previous Data Valid tOH Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC Address tAA CE# tACE CE2 OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5
(R)
LY622568
Rev. 2.2 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC Address tAW CE# tCW CE2 tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR
256K X 8 BIT LOW POWER CMOS SRAM
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC Address tAW CE# tAS tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR
Data Valid
Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE# VCC - 0.2V or CE2 0.2V LL VCC = 1.5V CE# VCC - 0.2V Data Retention Current IDR SL or CE2 0.2V Other pins at 0.2V or VCC-0.2V SL Chip Disable to Data See Data Retention tCDR Retention Time Waveforms (below) Recovery Time tR tRC* = Read Cycle Time MIN. 1.5 25 40
TYP. 1 1 1 1 -
MAX. 5.5 20 4 4 15 -
0 tRC*
UNIT V A A A A ns ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR 1.5V Vcc Vcc(min.) tCDR CE# VIH CE# Vcc-0.2V Vcc(min.) tR VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR 1.5V Vcc Vcc(min.) tCDR CE2 CE2 0.2V VIL VIL Vcc(min.) tR
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT SYM.
INCH(BASE) 0.047 (MAX) 0.004 0.002 0.039 0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 0.004 0.315 0.004 0.020 (TYP) 0.787 0.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.20 (MAX) 0.10 0.05 1.00 0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 0.10 8.00 0.10 0.50 (TYP) 20.00 0.20 0.50 0.10 0.08 0.10 0.076 (MAX) o o 0 5
A A1 A2 b c D E e HD L L1 y
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
c L
12 (2x)
1 32
12 (2x)
e
16 17
"A"
D Seating Plane
b
E
y
12 (2X)
16
17
GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE 12 (2X) L1 L
"A" DATAIL VIEW
1 32
UNIT SYM.
INCH(BASE) 0.049 (MAX) 0.005 0.002 0.039 0.002 0.008 0.01 0.005 (TYP) 0.465 0.004 0.315 0.004 0.020 (TYP) 0.5280.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.25 (MAX) 0.130 0.05 1.00 0.05 0.200.025 0.127 (TYP) 11.80 0.10 8.00 0.10 0.50 (TYP) 13.40 0.20. 0.50 0.10 0.8 0.10 0.076 (MAX) o o 0 5
A A1 A2 b c D E e HD L L1 y
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
32 pin 450 mil SOP Package Outline Dimension
UNIT SYM.
INCH.(BASE) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 0.005 0.555 0.012 0.050(TYP) 0.0347 0.008 0.055 0.008 0.026(MAX) 0.004(MAX) o o 0 -10
MM(REF) 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 0.127 14.097 0.305 1.270(TYP) 0.881 0.203 1.397 0.203 0.660 (MAX) 0.101(MAX) o o 0 -10
A A1 A2 b c D E E1 e L L1 S y
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
32 pin 600 mil P-DIP Package Outline Dimension
UNIT SYM.
INCH(BASE) 0.001 (MIN) 0.150 0.005 0.018 0.005 1.650 0.005 0.600 0.010 0.544 0.004 0.100 (TYP) 0.640 0.020 0.130 0.010 0.075 0.010 0.070 0.005
MM(REF) 0.254 (MIN) 3.810 0.127 0.457 0.127 41.910 0.127 15.240 0.254 13.818 0.102 2.540 (TYP) 16.256 0.508. 3.302 0.254 1.905 0.254 1.778 0.127
A1 A2 B D E E1 e eB L S Q1
Note : D/E1/S dimension do not include mold flash.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
LY622568 U V - WW XX Y Z
Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0C ~ 70C E : (Extended) -20C ~ +80C I : (Industrial) -40C ~ +85C XX : Power Type LL : Ultra Low Power SL : Special Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type L : 32-pin 8 mm x 20 mm TSOP-I R : 32-pin 8 mm x 13.4 mm STSOP S : 32-pin 450 mil SOP P : 32-pin 600 mil P-DIP
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12
(R)
LY622568
Rev. 2.2
256K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 13

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